1. Field of the Invention
The present invention relates generally to computer bus architectures, and more specifically to a virtual packet bus for packetized communications including a distributed arbitration technique with flexible prioritization.
2. Related Art
In digital computer systems having a plurality of modules, such as processor modules, controller modules, communications interface (relay) modules, etc., a medium is employed whereby these modules can transfer data among each other. Typically, the medium employed is a physical data channel known as a bus. The bus is connected to a communications port on each module. In typical data bus architectures, information is conveyed over the bus one word at a time. In addition, since there are multiple modules sharing the same bus, the modules must contend for bus access for each word sent.
A computer bus typically comprises multiple lines for transferring and for controlling the transfer of different types of information among the modules attached to the bus. Conventional bus architectures include a parallel data bus structure and multiple control lines. The data bus is typically N bits wide, where N is the number of bits per word.
Temporally, the bus is divided into a series of time slots known as bus cycles. A bus cycle is the period of time for which a module is granted access to the bus. In conventional bus architectures, the bus cycle is the same length as a clock cycle. Thus, in conventional systems, one N-bit word is transferred by a module on each clock cycle.
A common scenario in a computer system with a conventional bus architecture will now be described. A first module has a word or series of words that it wishes to send (or transfer) to a second module over the data bus. The first module signals that it wishes to access the bus. A means for arbitrating access to the bus determines whether the first module will be granted access on the next bus cycle. If access is not granted to the first module, the first module must repeat its request until access is granted. Once bus access is granted to the first module, it may send the first word to the second module via the bus. The same process must repeat again for each subsequent word the first module wishes to send. In some cases, limited forms of multiple word transfers by one module may be permitted.
Conventional bus architectures are limited in two respects. First, they are limited in that they allow only single-word transfers (or limited multiple-word transfers) for each bus cycle. Second, they are limited in the arbitration techniques employed to control access to the bus by the various modules.
These conventional bus architectures having single-word bus access provide the computer system with only limited communications flexibility, and do not provide optimum system performance in all environments. In certain environments, the computer system may be required to interface with various telecommunications networks. For example, the computer system may be implemented as a communications controller, controlling communications among the networks interfaced at a node. As an alternative example, the computer system may be used for scientific or business purposes and simply interfaced to the networks to obtain data.
Regardless of the underlying function of the computer in these environments, the computer is required to take data from, and sometimes put data onto, the various telecommunications networks to which it interfaces. These telecommunications networks typically operate on a packet level. That is, the networks transfer data in units defined as packets. The characteristics of the packet are defined according to the particular communications standard followed. Packets are typically defined as a specific number of bits in length, or a specific number of octets. For example, the Asynchronous Transfer Mode (ATM) communications specification has defined a 53-octet packet.
One word or limited multiple word transmission schemes implemented in conventional bus architectures are not directly compatible with these packet-level communications standards. If, for example, a packet of data is received at a network interface card, that packet cannot be directly sent across the conventional computer bus. Instead, the data must be `depacketized` (removed from the packet), sent across the bus one N-bit word at a time, and, if destined for further communications across another network, reassembled into packets. This incompatibility leads to a requirement for additional circuitry in the interface modules. This additional circuitry must allow interface cards to depacketize the data, reassemble the data into packets, and operate at both the packet level and the word level.
Conventional bus architectures are limited in their arbitration techniques. In many conventional systems, bus arbitration is handled by a central arbiter. In these systems, each module has a bus access request line and a line signalling the module when access is granted. Often, other control lines are added to provide additional information such as the state of the arbitration system. In systems using centralized arbitration, each module sends a bus access request to the central arbiter. Each access period, the central arbiter grants bus access to a module based on the priority of the requesting modules.
Other arbitration schemes have distributed the arbitration function to the modules attached to the bus. In these systems, arbitration circuitry is contained in each module, thus allowing the modules themselves to determine whether they are allowed access to the bus. Often these systems require arbitration busses to enable distributed arbitration. These arbitration busses are typically Y or 2Y lines wide, where Y is the number of modules. As with a centralized system, contention is resolved by evaluating the priority of the requesting systems and granting access to the requesting module with the highest priority.
Conventional arbitration techniques are limited in the manner in which module priority is assigned, thus restricting the flexibility of computer bus operations. This limitation is present in both centralized and distributed arbitration schemes. In conventional systems, priorities are assigned in various ways. First, priorities may be assigned based on a physical address, a bus location, or the card-slot location of the module. These priorities are fixed and cannot be changed unless the module is relocated or its address changed. Conventional arbitration schemes using this first type of prioritization technique sometimes allow flexibility by rotating the order of priority among the module locations.
A second method of assigning priorities in conventional systems is by making an initial assignment, and then rotating the priority of each module at the start of each subsequent bus cycle. In this method, each module starts with an initial priority. Each time access is granted to a module, module priorities shift. In some schemes, the priorities of each module are all incremented or decremented in a fixed manner.
Thus, conventional bus architectures are limited in two respects. They are limited in that they allow only for the transfer of a single word of data for each bus cycle. They are also limited in that the arbitration techniques employed provide limited flexibility in assignment and revision of module priorities. Additionally, conventional distributed arbitration techniques require arbitration buses with multiple signal paths, or the number of signal paths proportional to the number of modules on the bus.
Thus, conventional bus architectures are limited in the flexibility they provide for interfacing to external communication networks and are limited in their arbitration and module priority assignment techniques.